application note AN25 AN25-1 interfacing the x24c44/45 novrams to the motorola 6803 microcontroller by applications staff, july 1992 the following code demonstrates how the xicor x24c44/45 serial novrams can be interfaced to the motorola 6803 microcontroller when connected as shown in figure 1. the code uses three pins from port 1 to implement the interface. additional code can be found on the xicor web site at http://www.xicor.com that will implement interfaces between several other motorola microcontroller families and most xicor serial devices. vcc vcc u2 6803 x1 2 ex2 3 reset 6 nmi 4 irq1 5 p10 13 p11 14 p12 15 p13 16 p14 17 p15 18 p16 19 p17 20 p20 8 p21 9 p22 10 p23 11 p24 12 vccstb 21 p30 37 p31 36 p32 35 p33 34 p34 33 p35 32 p36 31 p37 30 p40 29 p41 28 p42 27 p43 26 p44 25 p45 24 p46 23 p47 22 sc1 39 sc2 38 e 40 u1 x24c44 di 3 ce 1 sk 2 recall 6 store 7 do 4 figure 1. interfacing an x24c44 to a 6803 microcontroller
xicor application note AN25-2 AN25 ******************************************************************************* * this code was designed to demonstrate how the x24c44 could be interfaced to * * the 6803 microcontroller. the interface uses 3 lines from port 1 (p17, * * p16, and p15) to communicate. the di and do pins on the x24c44 are tied * * together which allows 1 less port line to be used. * * * * the code shown demonstrates rcl, wren, read, write, and store * * instructions. the remaining instructions (wrds and enas) can be issued * * using the same routine as other non-data instructions. * * * * the program issues a sequence of instructions to read the contents of * * address 5 and stores the same value in address 9. the sequence of * * instructions is as follows : * * * * 1. rcl sets the previous recall latch * * 2. wren sets the write enable latch * * 3. read data from address 5 is read * * 4. write the data read during step 3 is written to address 9 * * 5. sto the ram's contents is transfered to the eeprom * * * * data transfer is performed with the most significant bit first. during * * the read and write instructions the data sequence is inverted from that * * shown in the data book (d15 is shifted first). * ******************************************************************************* skhi equ $20 mask to generate a 1 on sk sklo equ $df mask to generate a 0 on sk dihi equ $80 mask to generate a 1 on di dilo equ $7f mask to generate a 0 on di cehi equ $40 mask to generate a 1 on ce celo equ $bf mask to generate a 0 on ce wrds equ $80 reset write enable latch sto equ $81 transfers from ram to eeprom enas equ $82 places part into power down mode write equ $83 ram write wren equ $84 set write enable latch rcl equ $85 transfers from eeprom to ram, resets * write enable latch read equ $86 ram read ddr1 equ $00 data direction register for port 1 port1 equ $02 address for port 1 addr equ $80 location for x24c44 address to access inst equ $81 instruction for part rwdat equ $82 location for x24c44 data transfered p1data equ $84 data to be sent to dut dd1dat equ $85 data to be stored in port 1 direction register ********************************************* * reset vector to beginning of program code * ********************************************* org $fffe reset vector to program entry point fdb $e000
AN25-3 xicor application note AN25 ****************************** * start of program execution * ****************************** org $e000 beginning of executable code begin: lds #$00ff initialize stack pointer ldaa #$ff port 1 all outputs staa ddr1 initialize port1 direction register staa dd1dat initialize port1 direction value ldaa #$1f ce, sk, di all 0s staa port1 initialize port1 staa p1data initialize port1 data value ldaa #rcl perform a recall to set staa inst the recall latch jsr cehigh jsr outbyt jsr celow ldaa #wren perform a write enable to set staa inst the write enable latch jsr cehigh jsr outbyt jsr celow ldaa #$05 read the contents of address 5 staa addr the value read will be in stored jsr rdwrd in rwdata ldaa #$09 write the data just read into staa addr address 9 jsr wrwrd ldaa #sto perform a store operation staa inst jsr cehigh jsr outbyt jsr celow bra * loop until reset ****************************************************** * write the word specified in rwdat. the address to * * be written is specified in addr. * ****************************************************** wrwrd: jsr cehigh write value in rwdata into location ldaa addr specified in addr lsla justify address in instruction lsla lsla oraa #write mask in write instruction staa inst jsr outbyt send write instruction to dut ldaa rwdat staa inst jsr outbyt send in upper byte of data ldaa rwdat+1 staa inst
xicor application note AN25-4 AN25 jsr outbyt send in lower byte of data jsr celow rts ********************************************************* * read the word at the location specified in addr. the * * data read will be placed in rwdat. * ********************************************************* rdwrd: jsr cehigh read the address specified in addr ldaa addr lsla justify address to read lsla lsla oraa #read mask in read instruction staa inst jsr send7 send in 7 bits of read instruction ldaa dd1dat make data line an input anda #dilo staa ddr1 staa dd1dat jsr clock send eighth clock pulse for read instruction ldx #$0010 prepare to shift in 16 bits bitx: clc assume bit is going to be a zero (clear carry) ldaa port1 read bit value anda #dihi mask bit out of byte read beq no1 leave carry flag alone if bit is a 0 sec set carry if bit is a 1 no1: rol rwdat+1 roll carry flag into data word rol rwdat jsr clock send a clock pulse dex loop until bne bitx 16 bits are read ldaa dd1dat make data line an output oraa #dihi staa ddr1 staa dd1dat jsr celow rts ****************************************************** * send data out to the part. the data to be sent is * * located in inst. * ****************************************************** send7: ldx #$0007 shift out 7 bits for read instruction bra loopo outbyt:ldx #$0008 prepare to shift out 8 bits loopo: ldab p1data andb #dilo rol inst bcc is0 jump if data should be 0 orab #dihi make data a 1 is0: stab port1 put data on sda stab p1data
AN25-5 xicor application note AN25 jsr clock send clock signal dex bne loopo loop until all 8 bits have been sent rts ***************** * bring ce high * ***************** cehigh:ldaa p1data bring ce high oraa cehi staa port1 staa p1data rts **************** * bring ce low * **************** celow: ldaa p1data bring ce low anda celo staa port1 staa p1data rts ************************ * issue a clock pulse. * ************************ clock: ldaa p1data provide a clock pulse on sk oraa #skhi staa port1 bring sk high anda #sklo staa port1 bring sk low staa p1data rts
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